This application claims the priority of Korean Patent Application No. 03-92563, filed on Dec. 17, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a microcontroller, and more specifically, to an advanced microcontroller bus architecture (AMBA) system with reduced power consumption and a method of driving the AMBA system.
2. Description of the Related Art
In a the AMBA bus specification, developed by ARM Ltd., buses having different topologies, such as an advanced high-performance system bus (AHB), an advanced system bus (ASB), an advanced peripheral bus (APB), etc. are defined. Specifically, the advanced high-performance system bus (AHB) has a bus topology widely used in embedded microcontroller systems requiring high performance. In the above bus architectures, a bus signal is shared by many loads, and thus a large amount of power is wastefully consumed when a signal transition occurs in loads having no relation to a transfer path of a signal.
FIG. 1 is a block diagram illustrating an AHB topology of a conventional AMBA. In FIG. 1, bus signals such as address bus signals HADDR, and other bus signals HSIG such as transfer type signals, transfer direction signals, transfer size signals, burst type signals, and protection control signals, which are output from masters 111 to 114, are shared with slaves 131 to 134 under control of an arbiter signal HMASTER. Write data HWDATA output from the masters 111 to 114 are shared with the slaves 131 to 134 under control of an arbiter signal rHMASTER controlling a second multiplexer 122. Similarly, read data HRDATA, transfer ready signals HREADY, and transfer response signals HRESP, which are output from the slaves 131 to 134, are shared with the masters 111 to 114 under control of a decoder signal rHSEL controlling a third multiplexer 123.
FIG. 2 is a block diagram illustrating a capacitive load model of a write data bus of FIG. 1. In FIG. 2, the write data HWDATA are shared with the slaves 131 to 134 under control of the arbiter signal rHMASTER controlling the second multiplexer 122. For example, in the conventional AMBA, a signal transition occurs in all of buffer input loads CG1 to CG4, signal line loads CW1 to CW4, and slave input loads CL1 to CL4 at stages next to the second multiplexer 122, on transfer paths of bus signals for writing data. That is, the signal transition occurs in the overall capacitive loads on the paths with which the bus signals are shared. For this reason, when the write data HWDATA are transferred to a first slave 131 from a first master 111, any signal transitions that occur in the transfer also occur in the capacitive loads on the parallel paths routed toward the second slave 132, third slave 133 and fourth slave 134, which have no relation to the data write operation. Any signal transition that occurs in a load consumes power. Therefore, there is a problem that power is consumed wastefully due to the signal transitions occurring in the loads having no relation to transfer of the corresponding signals in the conventional AMBA. In addition, when the bus signals such as the read data HRDATA, the transfer ready signals HREADY, and the transfer response signals HRESP are transferred to the first master 111 from the first slave 131 so as to read out data, the corresponding bus signals are likewise transferred to and shared with all the masters 111 to 114, and thus these signal transitions also occur in all the loads on the transfer paths, thereby causing additional wasteful power consumption.